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| 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR * Two Instructions/Clock Sustained Execution * Four 59 Mbytes/s DMA Channels with Data Chaining * Demultiplexed 32-bit Burst Bus with Pipelining s 32-bit Parallel Architecture s Four On-Chip DMA Channels s s s s -- Two Instructions/clock Execution -- Load/Store Architecture -- Sixteen 32-bit Global Registers -- Sixteen 32-bit Local Registers -- Manipulates 64-bit Bit Fields -- 11 Addressing Modes -- Full Parallel Fault Model -- Supervisor Protection Model Fast Procedure Call/Return Model -- Full Procedure Call in 4 Clocks On-Chip Register Cache -- Caches Registers on Call/Ret -- Minimum of 6 Frames Provided -- Up to 15 Programmable Frames On-Chip Instruction Cache -- 1 Kbyte Two-Way Set Associative -- 128-bit Path to Instruction Sequencer -- Cache-Lock Modes -- Cache-Off Mode High Bandwidth On-Chip Data RAM -- 1 Kbyte On-Chip Data RAM -- Sustains 128 bits per Clock Access -- 59 Mbytes/s Fly-by Transfers -- 32 Mbytes/s Two-Cycle Transfers -- Data Chaining -- Data Packing/Unpacking -- Programmable Priority Method s 32-Bit Demultiplexed Burst Bus -- 128-bit Internal Data Paths to and from Registers -- Burst Bus for DRAM Interfacing -- Address Pipelining Option -- Fully Programmable Wait States -- Supports 8-, 16- or 32-bit Bus Widths -- Supports Unaligned Accesses -- Supervisor Protection Pin s Selectable Big or Little Endian Byte Ordering s High-Speed Interrupt Controller -- -- -- -- -- -- Up to 248 External Interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four Internal DMA Interrupts Separate, Non-maskable Interrupt Pin Context Switch in 750 ns Typical Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. (c) INTEL CORPORATION, 1993 November 1993 Order Number: 270727-006 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR CONTENTS PAGE 1.0 PURPOSE .................................................................................................................................................. 1 2.0 80960CA OVERVIEW................................................................................................................................. 1 2.1 The C-Series Core ..............................................................................................................................2 2.2 Pipelined, Burst Bus ...........................................................................................................................2 2.3 Flexible DMA Controller ......................................................................................................................2 2.4 Priority Interrupt Controller ..................................................................................................................2 2.5 Instruction Set Summary ....................................................................................................................3 3.0 PACKAGE INFORMATION.........................................................................................................................4 3.1 Package Introduction ..........................................................................................................................4 3.2 Pin Descriptions .................................................................................................................................. 4 3.3 80960CA Mechanical Data ............................................................................................................... 11 3.3.1 80960CA PGA Pinout ............................................................................................................ 11 3.3.2 80960CA PQFP Pinout .......................................................................................................... 15 3.4 Package Thermal Specifications ...................................................................................................... 18 3.5 Stepping Register Information .......................................................................................................... 20 3.6 Suggested Sources for 80960CA Accessories.................................................................................. 20 4.0 ELECTRICAL SPECIFICATIONS............................................................................................................. 21 4.1 Absolute Maximum Ratings .............................................................................................................. 21 4.2 Operating Conditions ........................................................................................................................ 21 4.3 Recommended Connections ............................................................................................................ 21 4.4 DC Specifications ............................................................................................................................. 22 4.5 AC Specifications .............................................................................................................................. 23 4.5.1 AC Test Conditions ................................................................................................................ 29 4.5.2 AC Timing Waveforms ........................................................................................................... 29 4.5.3 Derating Curves ..................................................................................................................... 33 5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE ................................................................................. 35 6.0 BUS WAVEFORMS ................................................................................................................................. 36 7.0 REVISION HISTORY ................................................................................................................................ 64 ii CONTENTS LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 PAGE 80960CA Block Diagram .............................................................................................................. 1 80960CA PGA Pinout--View from Top (Pins Facing Down) ...................................................... 13 80960CA PGA Pinout --View from Bottom (Pins Facing Up) .................................................... 14 80960CA PQFP Pinout (View from Top Side) ............................................................................ 17 Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18 Register g0 ................................................................................................................................. 20 AC Test Load .............................................................................................................................. 29 Input and Output Clocks Waveform ............................................................................................ 29 CLKIN Waveform ........................................................................................................................ 29 Output Delay and Float Waveform ............................................................................................. 30 Input Setup and Hold Waveform ................................................................................................ 30 NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31 Hold Acknowledge Timings ........................................................................................................ 31 Bus Backoff (BOFF) Timings ...................................................................................................... 32 Relative Timings Waveforms ...................................................................................................... 33 Output Delay or Hold vs. Load Capacitance .............................................................................. 33 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC .................. 34 ICC vs. Frequency and Temperature ........................................................................................... 34 Cold Reset Waveform ................................................................................................................ 36 Warm Reset Waveform .............................................................................................................. 37 Entering the ONCE State ........................................................................................................... 38 Clock Synchronization in the 2-x Clock Mode ............................................................................ 39 Clock Synchronization in the 1-x Clock Mode ............................................................................ 39 Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 40 Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 41 Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 42 Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43 Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44 Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ....................................... 45 Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46 Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 47 Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48 Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 49 Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 50 Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 51 Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52 Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53 Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54 iii CONTENTS LIST OF FIGURES (continued) Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 PAGE Using External READY ............................................................................................................... 55 Terminating a Burst with BTERM ............................................................................................... 56 BOFF Functional Timing ............................................................................................................ 57 HOLD Functional Timing ............................................................................................................ 58 DREQ and DACK Functional Timing .......................................................................................... 59 EOP Functional Timing .............................................................................................................. 59 Terminal Count Functional Timing .............................................................................................. 60 FAIL Functional Timing ............................................................................................................... 60 A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................ 61 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............ 62 Idle Bus Operation ...................................................................................................................... 63 LIST OF TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 80960CA Instruction Set .............................................................................................................. 3 Pin Description Nomenclature ...................................................................................................... 4 80960CA Pin Description -- External Bus Signals ...................................................................... 5 80960CA Pin Description -- Processor Control Signals .............................................................. 8 80960CA Pin Description -- DMA and Interrupt Unit Control Signals ....................................... 10 80960CA PGA Pinout -- In Signal Order ................................................................................... 11 80960CA PGA Pinout -- In Pin Order ........................................................................................ 12 80960CA PQFP Pinout -- In Signal Order ................................................................................. 15 80960CA PQFP Pinout -- In Pin Order ..................................................................................... 16 Maximum TA at Various Airflows in oC (PGA Package Only) ..................................................... 18 80960CA PGA Package Thermal Characteristics ...................................................................... 19 80960CA PQFP Package Thermal Characteristics .................................................................... 19 Die Stepping Cross Reference ................................................................................................... 20 Operating Conditions (80960CA-33, -25, -16) ............................................................................ 21 DC Characteristics ..................................................................................................................... 22 80960CA AC Characteristics (33 MHz) ...................................................................................... 23 80960CA AC Characteristics (25 MHz) ...................................................................................... 25 80960CA AC Characteristics (16 MHz) ...................................................................................... 27 Reset Conditions ........................................................................................................................ 35 Hold Acknowledge and Backoff Conditions ................................................................................ 35 iv 80960CA-33, -25, -16 1.0 PURPOSE This document provides electrical characteristics for the 33, 25 and 16 MHz versions of the 80960CA. For a detailed description of any 80960CA functional topic--other than parametric performance--consult the 80960CA Product Overview (Order No. 270669) or the i960(R) CA Microprocessor User's Manual (Order No. 270710). To obtain data sheet updates and errata, please call Intel's FaxBACK(R) data-ondemand system (1-800-628-2283 or 916-356-3105). Other information can be obtained from Intel's technical BBS (916-356-3600). A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system's high-speed external memory sub-system. In addition, the 80960CA's on-chip caching of instructions, procedure context and critical program data substantially decouple system performance from the wait states associated with accesses to the system's slower, cost sensitive, main memory subsystem. The 80960CA bus controller integrates full wait state and bus width control for highest system performance with minimal system design complexity. Unaligned access and Big Endian byte order support reduces the cost of porting existing applications to the 80960CA. The processor also integrates four complete datachaining DMA channels and a high-speed interrupt controller on-chip. DMA channels perform: singlecycle or two-cycle transfers, data packing and unpacking and data chaining. Block transfers--in addition to source or destination synchronized transfers--are provided. The interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch ("latency") time of 750 ns. 2.0 80960CA OVERVIEW The 80960CA is the second-generation member of the 80960 family of embedded processors. The 80960CA is object code compatible with the 32-bit 80960 Core Architecture while including Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instructions every clock and peak at execution of three instructions per clock. Instruction Prefetch Queue Instruction Cache (1 KByte, Two-way Set Associative) 128-BIT CACHE BUS Interrupt Programmable Port Interrupt Controller Multiply/Divide Unit Execution Unit Register-side Machine Bus Memory-side Machine Bus Parallel Instruction Scheduler Four-Channel DMA Controller Memory Region Configuration Bus Controller Bus Request Queues 1 KByte Data RAM 5 to 15 Sets Register Cache DMA Port Control Address Data Six-port Register File 64-Bit SRC1 Bus 64-Bit SRC2 Bus 64-Bit DST Bus 32-Bit Base Bus 128-Bit Load Bus 128-Bit Store Bus Address Generation Unit F_CX001A Figure 1. 80960CA Block Diagram 1 80960CA-33, -25, -16 2.1 The C-Series Core * * * * * * * Demultiplexed, Burst Bus to exploit most efficient DRAM access modes Address Pipelining to reduce memory cost while maintaining performance 32-, 16- and 8-bit modes for I/O interfacing ease Full internal wait state generation to reduce system cost Little and Big Endian support to ease application development Unaligned access support for code portability Three-deep request queue to decouple the bus from the core The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture. The C-Series core can sustain execution of two instructions per clock (66 MIPs at 33 MHz). To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the implementation of the C-Series core. Factors that contribute to the core's performance include: * * * Parallel instruction decoding allows issuance of up to three instructions per clock Single-clock execution of most instructions Parallel instruction decode allows sustained, simultaneous execution of two single-clock instructions every clock cycle Efficient instruction pipeline minimizes pipeline break losses Register and resource scoreboarding allow simultaneous multi-clock instruction execution Branch look-ahead and prediction allows many branches to execute with no pipeline break Local Register Cache integrated on-chip caches Call/Return context Two-way set associative, 1 Kbyte integrated instruction cache 1 Kbyte integrated Data RAM sustains a fourword (128-bit) access every clock cycle 2.3 Flexible DMA Controller * * * * * * A four-channel DMA controller provides high speed DMA control for data transfers involving peripherals and memory. The DMA provides advanced features such as data chaining, byte assembly and disassembly and a high performance fly-by mode capable of transfer speeds of up to 59 Mbytes per second at 33 MHz. The DMA controller features a performance and flexibility which is only possible by integrating the DMA controller and the 80960CA core. 2.4 Priority Interrupt Controller 2.2 Pipelined, Burst Bus A 32-bit high performance bus controller interfaces the 80960CA to external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 132 Mbytes per second (at 33 MHz). Internally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. The Bus Controller's main features include: A programmable-priority interrupt controller manages up to 248 external sources through the 8bit external interrupt port. The Interrupt Unit also handles the four internal sources from the DMA controller and a single non-maskable interrupt input. The 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered. Interrupts in the 80960CA are prioritized and signaled within 270 ns of the request. If the interrupt is of higher priority than the processor priority, the context switch to the interrupt routine typically is complete in another 480 ns. The interrupt unit provides the mechanism for the low latency and high throughput interrupt service which is essential for embedded applications. 2 80960CA-33, -25, -16 2.5 Instruction Set Summary Table 1 summarizes the 80960CA instruction set by logical groupings. See the i960(R) CA Microprocessor User's Manual for a complete description of the instruction set. Table 1. 80960CA Instruction Set Data Movement Load Store Move Load Address Add Subtract Multiply Divide Remainder Modulo Shift *Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Rotate Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls Mark Force Mark Processor Management Flush Local Registers Modify Arithmetic Controls Modify Process Controls *System Control *DMA Control NOTES: Instructions marked by (*) are 80960CA extensions to the 80960 instruction set. Arithmetic And Logical Bit and Bit Field and Byte Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Branch Unconditional Branch Conditional Branch Compare and Branch Call Call/Return Call Extended Call System Return Branch and Link Fault Conditional Fault Synchronize Faults Atomic Atomic Add Atomic Modify 3 80960CA-33, -25, -16 3.0 3.1 PACKAGE INFORMATION Package Introduction I Table 2. Pin Description Nomenclature Symbol Input only pin Output only pin Pin can be either an input or output Pins "must be" connected as described Synchronous. Inputs must meet setup and hold times relative to PCLK2:1 for proper operation. All outputs are synchronous to PCLK2:1. S(E) Edge sensitive input S(L) Level sensitive input Asynchronous. Inputs may be asynchronous to PCLK2:1. A(E) Edge sensitive input A(L) Level sensitive input While the processor's bus is in the Hold Acknowledge or Bus Backoff state, the pin: H(1) is driven to VCC H(0) is driven to VSS H(Z) floats H(Q) continues to be a valid input While the processor's RESET pin is low, the pin: R(1) is driven to VCC R(0) is driven to VSS R(Z) floats R(Q) continues to be a valid output O I/O - S(...) Description This section describes the pins, pinouts and thermal characteristics for the 80960CA in the 168-pin Ceramic Pin Grid Array (PGA) package and the 196pin Plastic Quad Flat Package (PQFP). For complete package specifications and information, see the Packaging Handbook (Order No. 240800). 3.2 Pin Descriptions A(...) The 80960CA pins are described in this section. Table 2 presents the legend for interpreting the pin descriptions in the following tables. Pins associated with the 32-bit demultiplexed processor bus are described in Table 3. Pins associated with basic processor configuration and control are described in Table 4. Pins associated with the 80960CA DMA Controller and Interrupt Unit are described in Table 5. All pins float while the processor is in the ONCE mode. H(...) R(...) 4 80960CA-33, -25, -16 Table 3. 80960CA Pin Description -- External Bus Signals (Sheet 1 of 3) Name A31:2 Type O S H(Z) R(Z) I/O S(L) H(Z) R(Z) O S H(Z) R(1) Description ADDRESS BUS carries the physical address' upper 30 bits. A31 is the most significant address bit; A2 is the least significant. During a bus access, A31:2 identify all external addresses to word (4-byte) boundaries. The byte enable signals indicate the selected byte in each word. During burst accesses, A3:2 increment to indicate successive data cycles. DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration. The least significant bit of the data is carried on D0 and the most significant on D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used. BYTE ENABLES select which of the four bytes addressed by A31:2 are active during an access to a memory region configured for a 32-bit data-bus width. BE3 applies to D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0. 32-bit bus: BE3 BE2 BE1 BE0 -Byte Enable 3 -Byte Enable 2 -Byte Enable 1 -Byte Enable 0 -enable D31:24 -enable D23:16 -enable D15:8 -enable D7:0 D31:0 BE3:0 For accesses to a memory region configured for a 16-bit data-bus width, the processor uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively. 16-bit bus: BE3 BE2 BE1 BE0 -Byte High Enable (BHE) -Not used (driven high or low) -Address Bit 1 (A1) -Byte Low Enable (BLE) -enable D7:0 -enable D15:8 For accesses to a memory region configured for an 8-bit data-bus width, the processor uses the BE1 and BE0 pins as A1 and A0 respectively. 8-bit bus: BE3 BE2 BE1 BE0 W/R O S H(Z) R(0) O S H(Z) R(1) -Not used (driven high or low) -Not used (driven high or low) -Address Bit 1 (A1) -Address Bit 0 (A0) WRITE/READ is asserted for read requests and deasserted for write requests. The W/R signal changes in the same clock cycle as ADS. It remains valid for the entire access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be valid in the last cycle of a read access. ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS is asserted for the first clock of a bus access. ADS 5 80960CA-33, -25, -16 Table 3. 80960CA Pin Description -- External Bus Signals (Sheet 2 of 3) Name READY Type I S(L) H(Z) R(Z) Description READY is an input which signals the termination of a data transfer. READY is used to indicate that read data on the bus is valid or that a write-data transfer has completed. The READY signal works in conjunction with the internally programmed wait-state generator. If READY is enabled in a region, the pin is sampled after the programmed number of wait-states has expired. If the READY pin is deasserted, wait states continue to be inserted until READY becomes asserted. This is true for the NRAD, NRDD, NWAD and NWDD wait states. The NXDA wait states cannot be extended. BURST TERMINATE is an input which breaks up a burst access and causes another address cycle to occur. The BTERM signal works in conjunction with the internally programmed wait-state generator. If READY and BTERM are enabled in a region, the BTERM pin is sampled after the programmed number of wait states has expired. When BTERM is asserted, a new ADS signal is generated and the access is completed. The READY input is ignored when BTERM is asserted. BTERM must be externally synchronized to satisfy BTERM setup and hold times. WAIT indicates internal wait state generator status. WAIT is asserted when wait states are being caused by the internal wait state generator and not by the READY or BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT can also be thought of as a READY output that the processor provides when it is inserting wait states. BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last data transfer of burst and non-burst accesses after the wait state counter reaches zero. BLAST remains asserted until the clock following the last cycle of the last data transfer of a bus access. If the READY or BTERM input is used to extend wait states, the BLAST signal remains asserted until READY or BTERM terminates the access. DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in conjunction with DEN to provide control for data transceivers attached to the external bus. When DT/R is asserted, the signal indicates that the processor receives data. Conversely, when deasserted, the processor sends data. DT/R changes only while DEN is high. DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of the bus request first data cycle and is deasserted at the end of the last data cycle. DEN is used in conjunction with DT/R to provide control for data transceivers attached to the external bus. DEN remains asserted for sequential reads from pipelined memory regions. DEN is deasserted when DT/R changes. BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK may be used to prevent external agents from accessing memory which is currently involved in an atomic operation. LOCK is asserted in the first clock of an atomic operation and deasserted in the clock cycle following the last bus access for the atomic operation. To allow the most flexibility for memory system enforcement of locked accesses, the processor acknowledges a bus hold request when LOCK is asserted. The processor performs DMA transfers while LOCK is active. HOLD REQUEST signals that an external agent requests access to the external bus. The processor asserts HOLDA after completing the current bus request. HOLD, HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents. BTERM I S(L) H(Z) R(Z) WAIT O S H(Z) R(1) O S H(Z) R(0) O S H(Z) R(0) O S H(Z) R(1) O S H(Z) R(1) BLAST DT/R DEN LOCK HOLD I S(L) H(Z) R(Z) 6 80960CA-33, -25, -16 Table 3. 80960CA Pin Description -- External Bus Signals (Sheet 3 of 3) Name BOFF Type I S(L) H(Z) R(Z) O S H(1) R(Q) Description BUS BACKOFF, when asserted, suspends the current access and causes the bus pins to float. When BOFF is deasserted, the ADS signal is asserted on the next clock cycle and the access is resumed. HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relinquished control of the external bus. When HOLDA is asserted, the external address bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents. Since the processor grants HOLD requests and enters the Hold Acknowledge state even while RESET is asserted, the state of the HOLDA pin is independent of the RESET pin. BUS REQUEST is asserted when the bus controller has a request pending. BREQ can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to determine when to return mastership of the external bus to the processor. DATA OR CODE is asserted for a data request and deasserted for instruction requests. D/C has the same timing as W/R. HOLDA BREQ O S H(Q) R(0) O S H(Z) R(Z) O S H(Z) R(Z) O S H(Z) R(Z) D/C DMA DMA ACCESS indicates whether the bus request was initiated by the DMA controller. DMA is asserted for any DMA request. DMA is deasserted for all other requests. SUP SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor mode. SUP is asserted when the request has supervisor privileges and is deasserted otherwise. SUP can be used to isolate supervisor code and data structures from non-supervisor requests. 7 80960CA-33, -25, -16 Table 4. 80960CA Pin Description -- Processor Control Signals (Sheet 1 of 2) Name RESET Type I A(L) H(Z) R(Z) Description RESET causes the chip to reset. When RESET is asserted, all external signals return to the reset state. When RESET is deasserted, initialization begins. When the 2-x clock mode is selected, RESET must remain asserted for 32 CLKIN cycles before being deasserted to guarantee correct processor initialization. When the 1-x clock mode is selected, RESET must remain asserted for 10,000 CLKIN cycles before being deasserted to guarantee correct processor initialization. The CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin. The processor's Hold Acknowledge bus state functions while the chip is reset. If the processor's bus is in the Hold Acknowledge state when RESET is asserted, the processor will internally reset, but maintains the Hold Acknowledge state on external pins until the Hold request is removed. If a Hold request is made while the processor is in the reset state, the processor bus will grant HOLDA and enter the Hold Acknowledge state. FAIL O S H(Q) R(0) FAIL indicates failure of the processor's self-test performed at initialization. When RESET is deasserted and the processor begins initialization, the FAIL pin is asserted. An internal self-test is performed as part of the initialization process. If this self-test passes, the FAIL pin is deasserted; otherwise it remains asserted. The FAIL pin is reasserted while the processor performs an external bus self-confidence test. If this self-test passes, the processor deasserts the FAIL pin and branches to the user's initialization routine; otherwise the FAIL pin remains asserted. Internal self-test and the use of the FAIL pin can be disabled with the STEST pin. SELF TEST causes the processor's internal self-test feature to be enabled or disabled at initialization. STEST is read on the rising edge of RESET. When asserted, the processor's internal self-test and external bus confidence tests are performed during processor initialization. When deasserted, only the bus confidence tests are performed during initialization. ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE is continuously sampled while RESET is low and is latched on the rising edge of RESET. To place the processor in the ONCE state: (1) assert RESET and ONCE (order does not matter) (2) wait for at least 16 CLKIN periods in 2-x mode--or 10,000 CLKIN periods in 1-x mode--after VCC and CLKIN are within operating specifications (3) (4) deassert RESET wait at least 32 CLKIN periods STEST I S(L) H(Z) R(Z) I A(L) H(Z) R(Z) ONCE (The processor will now be latched in the ONCE state as long as RESET is high.) To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert RESET and bring ONCE high prior to deasserting RESET. CLKIN must operate within the specified operating conditions of the processor until Step 4 above has been completed. CLKIN may then be changed to DC to achieve the lowest possible ONCE mode leakage current. ONCE can be used by emulator products or for board testers to effectively make an installed processor transparent in the board. 8 80960CA-33, -25, -16 Table 4. 80960CA Pin Description -- Processor Control Signals (Sheet 2 of 2) Name CLKIN Type I A(E) H(Z) R(Z) I A(L) H(Z) R(Z) Description CLOCK INPUT is an input for the external clock needed to run the processor. The external clock is internally divided as prescribed by the CLKMODE pin to produce PCLK2:1. CLOCK MODE selects the division factor applied to the external clock input (CLKIN). When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the processor's internal clock. When CLKMODE is low, CLKIN is divided by two to create PCLK2:1 and the processor's internal clock. CLKMODE should be tied high or low in a system as the clock mode is not latched by the processor. If left unconnected, the processor will internally pull the CLKMODE pin low, enabling the 2-x clock mode. PROCESSOR OUTPUT CLOCKS provide a timing reference for all processor inputs and outputs. All input and output timings are specified in relation to PCLK2 and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow flexibility in the system's allocation of capacitive loading on the clock. PCLK2:1 may also be connected at the processor to form a single clock signal. GROUND connections must be connected externally to a VSS board plane. POWER connections must be connected externally to a VCC board plane. VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode. Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in noisy environments. Otherwise, VCCPLL should be connected to VCC. This pin is implemented starting with the D-stepping. See Table 13 for die stepping information. NO CONNECT pins must not be connected in a system. CLKMODE PCLK2:1 O S H(Q) R(Q) - - - VSS V CC V CCPLL NC - 9 80960CA-33, -25, -16 Table 5. 80960CA Pin Description -- DMA and Interrupt Unit Control Signals Name DREQ3:0 Type I A(L) H(Z) R(Z) O S H(1) R(1) I/O A(L) H(Z/Q) R(Z) Description DMA REQUEST causes a DMA transfer to be requested. Each of the four signals requests a transfer on a single channel. DREQ0 requests channel 0, DREQ1 requests channel 1, etc. When two or more channels are requested simultaneously, the channel with the highest priority is serviced first. The channel priority mode is programmable. DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of the four signals acknowledges a transfer for a single channel. DACK0 acknowledges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted when the requesting device of a DMA is accessed. END OF PROCESS/TERMINAL COUNT can be programmed as either an input (EOP3:0) or as an output (TC3:0), but not both. Each pin is individually programmable. When programmed as an input, EOPx causes the termination of a current DMA transfer for the channel corresponding to the EOPx pin. EOP0 corresponds to channel 0, EOP1 corresponds to channel 1, etc. When a channel is configured for source and destination chaining, the EOP pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred. EOP3:0 are asynchronous inputs. When programmed as an output, the channel's TCx pin indicates that the channel byte count has reached 0 and a DMA has terminated. TCx is driven with the same timing as DACKx during the last DMA transfer for a buffer. If the last bus request is executed as multiple bus accesses, TCx will stay asserted for the entire bus request. XINT7:0 I A(E/L) H(Z) R(Z) EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can be configured in three modes: Dedicated Mode: each pin is a dedicated external interrupt source. Dedicated inputs can be individually programmed to be level (low) or edge (falling) activated. the eight pins act together as an 8-bit vectored interrupt source. The interrupt pins in this mode are level activated.Since the interrupt pins are active low, the vector number requested is the one's complement of the positive logic value place on the port. This eliminates glue logic to interface to combinational priority encoders which output negative logic. XINT7:5 are dedicated sources and XINT4:0 act as the five most significant bits of an expanded mode vector. The least significant bits are set to 010 internally. DACK3:0 EOP/TC3:0 Expanded Mode: Mixed Mode: NMI I A(E) H(Z) R(Z) NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated source. 10 80960CA-33, -25, -16 3.3 3.3.1 80960CA Mechanical Data 80960CA PGA Pinout Tables 6 and 7 list the 80960CA pin names with package location. Figure 2 depicts the complete 80960CA PGA pinout as viewed from the top side of the component (i.e., pins facing down). Figure 3 shows the complete 80960CA PGA pinout as viewed from the pin-side of the package (i.e., pins facing up). See Section 4.0, ELECTRICAL SPECIFICATIONS for specifications and recommended connections. Table 6. 80960CA PGA Pinout -- In Signal Order Address Bus Signal A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Pin S15 Q13 R14 Q14 S16 R15 S17 Q15 R16 R17 Q16 P15 P16 Q17 P17 N16 N17 M17 L16 L17 K17 J17 H17 G17 G16 F17 E17 E16 D17 D16 Data Bus Signal D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Pin R3 Q5 S2 Q4 R2 Q3 S1 R1 Q2 P3 Q1 P2 P1 N2 N1 M1 L1 L2 K1 J1 H1 H2 G1 F1 E1 F2 D1 E2 C1 D2 C2 E3 BOFF B1 D/C DMA SUP S13 R12 Q12 HOLD HOLDA BREQ R5 S4 R13 LOCK S14 DT/R DEN S11 S9 WAIT BLAST S12 S8 VSS Location C7, C8, C9, C10, C11, C12, F15, G3, G15, H3, H15, J3, J15, K3, K15, L3, L15, M3, M15, Q7, Q8, Q9, Q10, Q11 VCC Location B7, B9, B11, B12, C6, E15, F3, F16, G2, H16, J2, J16, K2, K16, M2, M16, N3, N15, Q6, R7, R8, R10, R11 VCCPLL Location A1, A3, A4, A5, B3, B4, C4, C5, D3 11 B10 No Connect XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 NMI C17 C16 B17 C15 B16 A17 A15 B15 D15 READY BTERM S3 R4 ADS R6 CLKIN CLKMODE PLCK1 PLCK2 C13 C14 B14 B13 EOP/TC3 EOP/TC2 EOP/TC1 EOP/TC0 A14 A13 A12 A11 W/R S10 ONCE C3 Bus Control Signal BE3 BE2 BE1 BE0 Pin S5 S6 S7 R9 STEST B2 DACK3 DACK2 DACK1 DACK0 A10 A9 A8 B8 FAIL A2 Processor Control Signal RESET Pin A16 DREQ3 DREQ2 DREQ1 DREQ0 I/O Signal Pin A7 B6 A6 B5 80960CA-33, -25, -16 Table 7. 80960CA PGA Pinout -- In Pin Order Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 Signal NC FAIL NC NC NC DREQ1 DREQ3 DACK1 DACK2 DACK3 EOP/TC0 EOP/TC1 EOP/TC2 EOP/TC3 XINT1 RESET XINT2 BOFF STEST NC NC DREQ0 DREQ2 VCC DACK0 VCC VCCPLL VCC VCC PCLK2 PCLK1 XINT0 XINT3 XINT5 F1 F2 F3 F15 F16 F17 12 D8 D6 VCC VSS VCC A6 E1 E2 E3 E15 E16 E17 D7 D4 D0 VCC A4 A5 L1 L2 L3 L15 L16 L17 D15 D14 VSS VSS A13 A12 Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 D17 Signal D3 D1 ONCE NC NC VCC VSS VSS VSS VSS VSS VSS CLKIN CLKMODE XINT4 XINT6 XINT7 D5 D2 NC NMI A2 A3 K1 K2 K3 K15 K16 K17 D13 VCC VSS VSS VCC A11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 D21 D23 D26 D28 D30 VCC VSS VSS VSS VSS VSS SUP A30 A28 A24 A21 A18 J1 J2 J3 J15 J16 J17 D12 VCC VSS VSS VCC A10 P1 P2 P3 P15 P16 P17 D19 D20 D22 A20 A19 A17 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 D25 D29 READY HOLDA BE3 BE2 BE1 BLAST DEN W/R DT/R WAIT D/C LOCK A31 A27 A25 H1 H2 H3 H15 H16 H17 D11 D10 VSS VSS VCC A9 N1 N2 N3 N15 N16 N17 D17 D18 VCC VCC A16 A15 Pin G1 G2 G3 G15 G16 G17 Signal D9 VCC VSS VSS A7 A8 Pin M1 M2 M3 M15 M16 M17 Signal D16 VCC VSS VSS VCC A14 Pin R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 Signal D24 D27 D31 BTERM HOLD ADS VCC VCC BE0 VCC VCC DMA BREQ A29 A26 A23 A22 80960CA-33, -25, -16 S 1 D25 R Q P N M L K J H G F E D C B A 1 D24 D21 D19 D17 D16 D15 D13 D12 D11 D9 D8 D7 D5 D3 BOFF NC 2 D29 D27 D23 D20 D18 V CC V SS D14 V CC V SS V CC V SS D10 V CC V SS D6 D4 D2 D1 STEST FAIL 2 3 READY D31 D26 D22 VCC V SS V SS V CC D0 NC ONCE NC NC 3 4 HOLDA BTERM D28 NC NC NC 4 5 BE3 HOLD D30 NC DREQ0 NC 5 6 BE2 ADS V CC V SS V SS V SS V SS V SS SUP VCC VSS VSS VSS VSS VSS VSS DREQ2 DREQ1 6 7 BE1 V CC V CC BE0 V CC DREQ3 7 8 BLAST DACK0 DACK1 8 9 DEN V CC DACK2 9 10 W/R V CC V CC DMA V CCPLL DACK3 10 11 DT/R V CC V CC EOP/TC0 11 12 WAIT EOP/TC1 12 13 D/C BREQ A30 CLKIN PCLK2 EOP/TC2 13 14 LOCK A29 A28 CLK MODE PCLK1 EOP/TC3 14 15 A31 A26 A24 A20 VCC A16 V SS V CC A14 V SS A13 V SS V CC A11 V SS V CC A10 V SS VCC A9 V SS A7 V SS V CC A6 V CC A4 NMI XINT4 XINT0 XINT1 15 16 A27 A23 A21 A19 A2 XINT6 XINT3 RESET 16 17 A25 A22 A18 A17 A15 A12 A8 A5 A3 XINT7 XINT5 XINT2 17 S R Q P N M L K J H G F E D C B A F_CA002A Figure 2. 80960CA PGA Pinout -- View from Top (Pins Facing Down) 13 80960CA-33, -25, -16 A 1 NC B C D E F G H J K L M N P Q R S 1 BOFF D3 D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25 2 FAIL STEST D1 D2 D4 D6 V CC V SS D10 V CC V SS V CC V SS D14 V CC V SS D18 D20 D23 D27 D29 2 3 NC NC ONCE NC D0 VCC V SS VSS V CC D22 D26 D31 READY 3 4 NC NC NC D28 BTERM HOLDA 4 5 NC DREQ0 NC D30 HOLD BE3 5 6 DREQ1 DREQ2 V CC V SS V SS V SS V SS V SS V SS VCC V SS V SS V SS ADS BE2 6 7 DREQ3 V CC V CC V CC BE0 BE1 7 8 DACK1 DACK0 8 9 DACK2 V CC Metal Lid BLAST 9 DEN 10 DACK3 V CCPLL V SS V SS SUP V CC V CC DMA W/R 10 11 EOP/TC0 V CC V CC DT/R 11 12 EOP/TC1 WAIT 12 13 EOP/TC2 PCLK2 CLKIN A30 BREQ D/C 13 14 EOP/TC3 PCLK1 CLK MODE A28 A29 LOCK 14 15 XINT1 XINT0 XINT4 NMI V CC A4 VSS V CC A6 V SS A7 V SS V CC A9 V SS V CC A10 V SS V CC A11 VSS A13 V SS V CC A14 V CC A16 A20 A24 A26 A31 15 16 RESET XINT3 XINT6 A2 A19 A21 A23 A27 16 17 XINT2 XINT5 XINT7 A3 A5 A8 A12 A15 A17 A18 A22 A25 17 A B C D E F G H J K L M N P Q R S F_CA003A Figure 3. 80960CA PGA Pinout -- View from Bottom (Pins Facing Up) 14 80960CA-33, -25, -16 3.3.2 80960CA PQFP Pinout See Section 4.0, ELECTRICAL SPECIFICATIONS for specifications and recommended connections. Tables 8 and 9 list the 80960CA pin names with package location. Figure 4 shows the 80960CA PQFP pinout as viewed from the top side. Table 8. 80960CA PQFP Pinout -- In Signal Order Address Bus Signal A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Pin 153 152 151 145 144 143 142 141 139 138 137 136 134 133 132 130 129 128 124 123 122 120 119 118 117 116 114 113 112 111 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Bus Signal Pin 186 187 188 189 191 192 194 195 3 4 5 6 8 9 10 11 13 14 15 17 18 19 21 22 23 25 26 27 33 34 35 36 15 BOFF 40 D/C DMA SUP 159 160 158 HOLD HOLDA BREQ 181 179 155 VCCPLL Location 29, 31, 41, 42, 47, 48, 51, 52, 53, 54, 55, 73, 76, 80, 84, 86, 90, 97, 104, 126, 146, 149, 157, 166, 177, 183, 193 72 NMI 108 No Connect LOCK 156 DT/R DEN 163 167 WAIT BLAST 162 169 READY BTERM 182 184 ADS 178 W/R 164 Bus Control Signal BE3 BE2 BE1 BE0 Pin 176 175 172 170 Processor Control Signal RESET FAIL STEST ONCE CLKIN CLKMODE PCLK2 PCLK1 V SS Location 2, 7, 16, 24, 30, 38, 39, 49, 56, 70, 75, 77, 81, 83, 88, 89, 92, 98, 105, 109, 110, 121, 125, 131, 135, 147, 150, 161, 165, 173, 174, 185, 196 VCC Location 1, 12, 20, 28, 32, 37, 44, 50, 61, 71, 79, 82, 96, 99, 103, 115, 127, 140, 148, 154, 168, 171, 180, 190 EOP/TC3 EOP/TC2 EOP/TC1 EOP/TC0 XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 69 68 67 66 107 106 102 101 100 95 94 93 Pin 91 45 46 43 87 85 74 78 DACK3 DACK2 DACK1 DACK0 65 64 63 62 I/O Signal DREQ3 DREQ2 DREQ1 DREQ0 Pin 60 59 58 57 80960CA-33, -25, -16 Table 9. 80960CA PQFP Pinout -- In Pin Order Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal VCC VSS D23 D22 D21 D20 VSS D19 D18 D17 D16 VCC D15 D14 D13 VSS D12 D11 D10 VCC D9 D8 D7 VSS D6 D5 D4 VCC NC VSS NC VCC D3 Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Signal D2 D1 D0 VCC VSS VSS BOFF NC NC ONCE VCC Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal EOP/TC1 EOP/TC2 EOP/TC3 VSS VCC VCCPLL NC PCLK2 VSS NC VSS PCLK1 VCC NC VSS VCC VSS NC CLKMODE NC CLKIN VSS VSS Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Signal XINT3 XINT4 XINT5 VCC NC VSS XINT6 XINT7 NMI VSS VSS A2 A3 A4 A5 VCC A6 A7 A8 A9 A10 VSS Pin 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 Signal A18 A19 VSS A20 A21 A22 A23 VCC A24 A25 A26 A27 A28 NC VSS VCC NC VSS A29 A30 A31 VCC BREQ LOCK NC SUP D/C Pin 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 Signal NC DEN VCC BLAST BE0 VCC BE1 VSS VSS BE2 BE3 NC ADS HOLDA VCC HOLD READY NC BTERM VSS D31 D30 D29 D28 VCC D27 D26 NC D25 D24 VSS FAIL STEST NC NC VSS V CC NC NC NC NC NC V SS DREQ0 DREQ1 DREQ2 DREQ3 VCC DACK0 DACK1 DACK2 DACK3 EOP/TC0 A11 A12 A13 VSS NC VCC NC RESET VSS XINT0 XINT1 XINT2 VCC NC VSS VCC DMA VSS WAIT DT/R W/R A14 A15 A16 VSS A17 VSS 16 80960CA-33, -25, -16 98 50 99 49 147 Pin 1 148 196 F_CA004A Figure 4. 80960CA PQFP Pinout (View from Top Side) 17 80960CA-33, -25, -16 3.4 Package Thermal Specifications TA = TC - P*CA Table 10 shows the maximum TA allowable (without exceeding TC) at various airflows and operating frequencies (fPCLK). Note that TA is greatly improved by attaching fins or a heatsink to the package. P (maximum power consumption) is calculated by using the typical ICC as tabulated in Section 4.4, DC Specifications and VCC of 5V. The 80960CA is specified for operation when TC (case temperature) is within the range of 0oC-100oC. TC may be measured in any environment to determine whether the 80960CA is within specified operating range. Case temperature should be measured at the center of the top surface, opposite the pins. Refer to Figure 5. TA (ambient temperature) can be calculated from CA (thermal resistance from case to ambient) using the following equation: Measure PGA temperature at center of top surface Measure PQFP case temperature at center of top surface. 168 - Pin PGA Pin 196 Pin 1 F_CX007A Figure 5. Measuring 80960CA PGA and PQFP Case Temperature Table 10. Maximum TA at Various Airflows in oC (PGA Package Only) Airflow-ft/min (m/sec) fPCLK (MHz) 33 TA with Heatsink* 25 16 33 TA without Heatsink* 25 16 0 (0) 51 61 74 36 49 66 200 (1.01) 66 73 82 47 58 72 400 (2.03) 79 83 89 59 67 78 600 (3.04) 81 85 90 66 73 82 800 (4.06) 85 88 92 73 78 86 1000 (5.07) 87 89 93 75 80 87 NOTES: *0.285" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). 18 80960CA-33, -25, -16 Table 11. 80960CA PGA Package Thermal Characteristics Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter Junction-to-Case (Case measured as shown in Figure 5) Case-to-Ambient (No Heatsink) Case-to-Ambient (With Heatsink)* 0 (0) 200 (1.01) 400 (2.03) 600 (3.07) 800 (4.06) 1000 (5.07) 1.5 1.5 1.5 1.5 1.5 1.5 JA JC 17 13 14 9 11 5.5 9 5 7.1 3.9 6.6 3.4 NOTES: 1. This table applies to 80960CA PGA plugged into socket or soldered directly to board. 2. JA = JC + CA *0.285" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Table 12. 80960CA PQFP Package Thermal Characteristics Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter Junction-to-Case (Case Measured as shown in Figure 5) Case-to-Ambient (No Heatsink) 0 (0) 5 19 50 (0.25) 5 18 100 (0.50) 5 17 200 (1.01) 5 15 400 (2.03) 5 12 600 (3.04) 5 10 800 (4.06) 5 9 NOTES: 1. This table applies to 80960CA PQFP soldered directly to board. 2. JA = JC + CA JC 19 80960CA-33, -25, -16 3.5 Stepping Register Information 3.6 Upon reset, register g0 contains die stepping information. Figure 6 shows how g0 is configured. The most significant byte contains an ASCII 0. The upper middle byte contains an ASCII C. The lower middle byte contains an ASCII A. The least significant byte contains the stepping number in ASCII. g0 retains this information until it is overwritten by the user program. Suggested Sources for 80960CA Accessories The following is a list of suggested sources for 80960CA accessories. This is not an endorsement of any kind, nor is it a warranty of the performance of any of the listed products and/or companies. Sockets 1. 3M Textool Test and Interconnection Products Department P.O. Box 2963 Austin, TX 78769-2963 2. Augat, Inc. Interconnection Products Group 33 Perry Avenue P.O. box 779 Attleboro, MA 02703 (508) 699-7646 3. Concept Manufacturing, Inc. (Decoupling Sockets) 41484 Christy Street Fremont, CA 94538 (415) 651-3804 Heatsinks/Fins 1. Thermalloy, Inc. 2021 West Valley View Lane Dallas, TX 75234-8993 (214) 243-4321 FAX: (214) 241-4656 2. E G & G Division 60 Audubon Road Wakefield, MA 01880 (617) 245-5900 ASCII DECIMAL 00 0 MSB 43 C 41 A Stepping Number Stepping Number LSB Figure 6. Register g0 Table 13 contains a cross reference of the number in the least significant byte of register g0 to the die stepping number. Table 13. Die Stepping Cross Reference g0 Least Significant Byte 01 02 03 04 Die Stepping B C-1 C-2,C-3 D 20 80960CA-33, -25, -16 4.0 4.1 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Maximum Rating NOTICE: This is a production data sheet. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Storage Temperature ................................-65oC to +150oC Case Temperature Under Bias .................-65oC to +110oC Supply Voltage wrt. VSS ............................. -0.5V to + 6.5V Voltage on Other Pins wrt. VSS ...........-0.5V to VCC + 0.5V 4.2 Operating Conditions Table 14. Operating Conditions (80960CA-33, -25, -16) Symbol VCC Supply Voltage Parameter 80960CA-33 80960CA-25 80960CA-16 80960CA-33 80960CA-25 80960CA-16 80960CA-33 80960CA-25 80960CA-16 PGA Package 196-Pin PQFP Min 4.75 4.50 4.50 0 0 0 8 8 8 0 0 Max 5.25 5.50 5.50 66.66 50 32 33.33 25 16 100 100 Units V V V MHz MHz MHz MHz MHz MHz oC oC Notes fCLK2x Input Clock Frequency (2-x Mode) fCLK1x Input Clock Frequency (1-x Mode) (1) TC Case Temperature Under Bias 80960CA-33, -25, -16 NOTES: 1. When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 MHz for proper processor operation. However, in the 1-x mode, CLKIN may still be stopped when the processor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once CLKIN restarts and has stabilized. 4.3 Recommended Connections Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every 80960CAbased circuit board should include power (VCC) and ground (VSS) planes for power distribution. Every V CC pin must be connected to the power plane, and every VSS pin must be connected to the ground plane. Pins identified as "NC" must not be connected in the system. Liberal decoupling capacitance should be placed near the 80960CA. The processor can cause transient power surges when its numerous output buffers transition, particularly when connected to large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by shortening the board traces between the processor and decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages will offer the lowest possible inductance. For reliable operation, always connect unused inputs to an appropriate signal level. In particular, any unused interrupt (XINT, NMI) or DMA (DREQ) input should be connected to VCC through a pull-up resistor, as should BTERM if not used. Pull-up resistors should be in the in the range of 20 K for each pin tied high. If READY or HOLD are not used, the unused input should be connected to ground. N.C. pins must always remain unconnected. Refer to the i960(R) Cx Microprocessor User's Manual (Order Number 270710) for more information. 21 80960CA-33, -25, -16 4.4 DC Specifications Table 15. DC Characteristics (80960CA-33, -25, -16 under the conditions described in Section 4.2, Operating Conditions.) Symbol Parameter Min Max Units Notes VIL VIH VOL VOH VILR VIHR ILI1 Input Low Voltage for all pins except RESET Input High Voltage for all pins except RESET Output Low Voltage Output High Voltage Input Low Voltage for RESET Input High Voltage for RESET Input Leakage Current for each pin except: BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, BOFF, READY, HOLD, CLKMODE Input Leakage Current for: BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, BOFF Input Leakage Current for: READY, HOLD, CLKMODE Output Leakage Current Supply Current (80960CA-33): ICC Max ICCTyp IOH = -1 mA IOH = - 200 A - 0.3 2.0 2.4 VCC - 0.5 - 0.3 3.5 +0.8 VCC + 0.3 0.45 V V V V V IOL = 5 mA 1.5 VCC + 0.3 V V 15 A 0 VIN VCC (1) VIN = 0.45V (2) VIN = 2.4V (3,7) 0.45 VOUT VCC (4) (5) (4) (5) (4) (5) ILI2 0 0 - 300 500 15 900 750 750 600 550 400 100 A A A mA mA mA mA mA mA mA ILI3 ILO ICC ICC Supply Current (80960CA-25): ICC Max ICCTyp ICC Supply Current (80960CA-16): ICC Max ICCTyp IONCE CIN ONCE-mode Supply Current Input Capacitance for: CLKIN, RESET, ONCE, READY, HOLD, DREQ3:0, BOFF, XINT7:0, NMI, BTERM, CLKMODE Output Capacitance of each output pin I/O Pin Capacitance 0 12 12 12 pF pF pF FC = 1 MHz FC = 1 MHz (6) FC = 1 MHz COUT CI/O NOTES: 1. No pullup or pulldown. 2. These pins have internal pullup resistors. 3. These pins have internal pulldown resistors. 4. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions described in Section 4.5.1, AC Test Conditions. 5. ICC Typical is not tested. 6. Output Capacitance is the capacitive load of a floating output. 7. CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted. 22 80960CA-33, -25, -16 4.5 AC Specifications Table 16. 80960CA AC Characteristics (33 MHz) (80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes Input Clock (1,9) CLKIN Frequency TF TC TCS TCH TCL TCR TCF CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) (T/2) - 2 (T/2) - 2 1 1 In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 0 30 15 6 6 6 6 0 0 -2 2 TC 2TC T/2 T/2 4 4 66.66 125 0.1% 62.5 62.5 6 6 2 25 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3,12) (3) (12) (3) (12) (12) (3) (3) (6,10) A31:2 BE3:0 ADS W/R D/C, SUP, DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 3 14 16 18 18 16 16 16 16 16 18 16 T/2 + 14 14 18 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (11) (12) (11) (11) Output Clocks (1,8) CLKIN to PCLK2:1 Delay TCP T TPH TPL TPR TPF PCLK2:1 Period PCLK2:1 High Time PCLK2:1 Low Time PCLK2:1 Rise Time PCLK2:1 Fall Time Synchronous Outputs (8) Output Valid Delay, Output Hold TOH TOV TOH1, TOV1 TOH2, TOV2 TOH3, TOV3 TOH4, TOV4 TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9, TOV9 TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14, TOV14 TOF Output Float for all outputs Synchronous Inputs (1,9,10) Input Setup TIS TIS1 TIS2 TIS3 TIS4 Input Hold TIH TIH1 TIH2 TIH3 TIH4 (6,10) (6) D31:0 BOFF BTERM/READY HOLD D31:0 BOFF BTERM/READY HOLD 3 17 7 7 5 5 2 3 ns ns ns ns ns ns ns ns 23 80960CA-33, -25, -16 Table 16. 80960CA AC Characteristics (33 MHz) (Continued) (80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes Relative Output Timings (1,2,3,8) TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV A31:2 Valid to ADS Rising BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising A31:2 Valid to DEN Falling BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT/R Hold after DEN High T-4 T-6 T-4 T-6 4 N*T - 4 N*T + 4 N*T 4 (N+1)*T-8 T/2 - 7 T/2 - 4 6 5 12 7 7 3 3 T/4 + 1 (N+1)*T+6 T+4 T+6 T+4 T+6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (13) (13) (7) (7) (15) (15) (14) (14) (4) (4) (5) (6) DT/R Valid to DEN Falling TTVEL Relative Input Timings (1,2,3) TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) DREQ3:0 Input Setup DREQ3:0 Input Hold XINT7:0, NMI Input Setup XINT7:0, NMI Input Hold RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) NOTES: 1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. 2. See Figure 16 for capacitive derating information for output delays and hold times. 3. See Figure 17 for capacitive derating information for rise and fall times. 4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes active when there are no wait states in an access. 5. N = Number of wait states inserted with READY. 6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. 8. These specifications are guaranteed by the processor. 9. These specifications must be met by the system for proper operation of the processor. 10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for PCLK2:1 loading. 11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. 12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than 0.1% between adjacent cycles. 13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 22.) 14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 23.) 15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges. 24 80960CA-33, -25, -16 Table 17. 80960CA AC Characteristics (25 MHz) (80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Input Clock (1,9) TF TC TCS TCH TCL TCR CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 8 8 8 8 0 0 In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) (T/2) - 3 (T/2) - 3 1 1 -2 2 TC 2TC T/2 T/2 4 4 0 40 20 50 125 0.1% 62.5 62.5 6 6 2 25 MHz ns ns (11) (12) (11) (11) Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLKIN Fall Time TCF Output Clocks (1,8) TCP T TPH TPL TPR CLKIN to PCLK2:1 Delay PCLK2:1 Period PCLK2:1 High Time PCLK2:1 Low Time PCLK2:1 Rise Time (3,12) (3) (12) (3) (12) (12) (3) (3) (6,10) PCLK2:1 Fall Time TPF Synchronous Outputs (8) TOH TOV Output Valid Delay, Output Hold TOH1, TOV1 TOH2, TOV2 TOH3, TOV3 TOH4, TOV4 TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9, TOV9 TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14, TOV14 Output Float for all outputs Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 A31:2 BE3:0 ADS W/R D/C, SUP, DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 TOF TIS 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 3 16 18 20 20 18 18 18 18 18 20 18 T/2 + 16 16 20 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6,10) (6) Synchronous Inputs (1,9,10) D31:0 BOFF BTERM/READY HOLD D31:0 BOFF BTERM/READY HOLD 5 19 9 9 5 7 2 5 ns ns ns ns ns ns ns ns TIH 25 80960CA-33, -25, -16 Table 17. 80960CA AC Characteristics (25 MHz) (Continued) (80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Relative Output Timings (1,2,3,8) TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV A31:2 Valid to ADS Rising BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising A31:2 Valid to DEN Falling BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT/R Hold after DEN High T-4 T-6 T-4 T-6 4 N*T - 4 N*T + 4 N*T 4 (N+1)*T-8 T/2 - 7 T/2 - 4 8 7 14 9 9 5 3 T/4 + 1 (N+1)*T+6 T+4 T+6 T+4 T+6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (13) (13) (7) (7) (15) (15) (14) (14) (4) (4) (5) (6) Notes DT/R Valid to DEN Falling TTVEL Relative Input Timings (1,2,3) TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) DREQ3:0 Input Setup DREQ3:0 Input Hold XINT7:0, NMI Input Setup XINT7:0, NMI Input Hold RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) NOTES: 1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. 2. See Figure 16 for capacitive derating information for output delays and hold times. 3. See Figure 17 for capacitive derating information for rise and fall times. 4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes active when there are no wait states in an access. 5. N = Number of wait states inserted with READY. 6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. 8. These specifications are guaranteed by the processor. 9. These specifications must be met by the system for proper operation of the processor. 10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for PCLK2:1 loading. 11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. 12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than 0.1% between adjacent cycles. 13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 22.) 14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 23.) 15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges. 26 80960CA-33, -25, -16 Table 18. 80960CA AC Characteristics (16 MHz) (80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes Input Clock (1,9) TF TC TCS TCH TCL TCR TCF TCP T TPH TPL TPR TPF TOH TOV CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to PCLK2:1 Delay PCLK2:1 Period PCLK2:1 High Time PCLK2:1 Low Time PCLK2:1 Rise Time PCLK2:1 Fall Time Output Valid Delay, Output Hold TOH1, TOV1 TOH2, TOV2 TOH3, TOV3 TOH4, TOV4 TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9, TOV9 TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14, TOV14 Output Float for all outputs Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) (T/2) - 4 (T/2) - 4 1 1 In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 0 62.5 31.25 10 10 10 10 0 0 -2 2 TC 2TC T/2 T/2 4 4 32 125 0.1% 62.5 62.5 6 6 2 25 MHz ns ns (11) (12) (11) (11) ns ns ns ns ns ns ns ns ns ns ns ns ns ns Output Clocks (1,8) (3,12) (3) (12) (3) (12) (12) (3) (3) (6,10) A31:2 BE3:0 ADS W/R D/C, SUP, DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 3 18 20 22 22 20 20 20 20 20 22 20 T/2 + 18 18 22 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Synchronous Outputs (8) (6,10) (6) TOF TIS Synchronous Inputs (1,9,10) D31:0 BOFF BTERM/READY HOLD D31:0 BOFF BTERM/READY HOLD 5 21 9 9 5 7 2 5 ns ns ns ns ns ns ns ns TIH 27 80960CA-33, -25, -16 Table 18. 80960CA AC Characteristics (16 MHz) (Continued) (80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes Relative Output Timings (1,2,3,8) TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 A31:2 Valid to ADS Rising BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising A31:2 Valid to DEN Falling BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT/R Hold after DEN High DT/R Valid to DEN Falling RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) DREQ3:0 Input Setup DREQ3:0 Input Hold XINT7:0, NMI Input Setup XINT7:0, NMI Input Hold RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) T-4 T-6 T-6 T-6 4 N*T - 4 (N+1)*T-8 T/2 - 7 T/2 - 4 10 9 16 11 9 5 3 T/4 + 1 N*T + 4 (N+1)*T+6 N*T 4 T+4 T+6 T+6 T+6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (13) (13) (7) (7) (15) (15) (14) (14) (4) (4) (5) (6) Relative Input Timings (1,2,3) NOTES: 1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. 2. See Figure 16 for capacitive derating information for output delays and hold times. 3. See Figure 17 for capacitive derating information for rise and fall times. 4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes active when there are no wait states in an access. 5. N = Number of wait states inserted with READY. 6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. 8. These specifications are guaranteed by the processor. 9. These specifications must be met by the system for proper operation of the processor. 10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for PCLK2:1 loading. 11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. 12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than 0.1% between adjacent cycles. 13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 22.) 14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 23.) 15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges. 28 80960CA-33, -25, -16 4.5.1 AC Test Conditions Output Pin The AC Specifications in Section 4.5 are tested with the 50 pF load shown in Figure 7. Figure 16 shows how timings vary with load capacitance. Specifications are measured at the 1.5V crossing point, unless otherwise indicated. Input waveforms are assumed to have a rise and fall time of 2 ns from 0.8V to 2.0V. See Section 4.5.2, AC Timing Waveforms for AC spec definitions, test points and illustrations. 4.5.2 AC Timing Waveforms CL CL = 50 pF for all signals F_CX008A Figure 7. AC Test Load CLKIN 1.5V TCP T PCLK2:1 1.5V 2.4V 1.5V 0.45V TPH TPR TPL TPF F_CX009A Figure 8. Input and Output Clocks Waveform TCR TCF 2.0V 1.5V 0.8V TCH TCL TC F_CX010A Figure 9. CLKIN Waveform 29 80960CA-33, -25, -16 PCLK2:1 1.5V 1.5V TOH Outputs 1.5V TOV Min Max 1.5V TOF Outputs 1.5V Min Max 1.5V F_CX011A Figure 10. Output Delay and Float Waveform PCLK2:1 1.5V 1.5V TIH Max Valid 1.5V TIS Min Inputs: (READY, HOLD, BTERM, BOFF, DREQ3:0, D31:0 on reads) F_CX012A Figure 11. Input Setup and Hold Waveform TOV TOH - OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (TOV). The minimum output delay is referred to as the Output Hold (TOH). TOF TIS TIH - OUTPUT FLOAT DELAY - The output float condition occurs when the maximum output current becomes less that ILO in magnitude. - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. 30 80960CA-33, -25, -16 PCLK2:1 1.5V 1.5V 1.5V Min NMI, XINT7:0 1.5V TIS TIH Min Valid 1.5V F_CX013A Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform PCLK2:1 1.5V 1.5V TOF Min Max 1.5V TOV Min Max Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA TIH Min HOLD 1.5V Valid 1.5V Valid TIS Min TIH Min 1.5V TIS Min 1.5V TOV TOV Min Max HOLDA 1.5V Min 1.5V Max 1.5V TOV TOH - OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (TOV). The minimum output delay is referred to as the Output Hold (TOH). TOF TIS TIH - OUTPUT FLOAT DELAY - The output float condition occurs when the maximum output current becomes less that ILO in magnitude. - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. F_CX014A Figure 13. Hold Acknowledge Timings 31 80960CA-33, -25, -16 PCLK2:1 1.5V 1.5V TOF Min 1.5V TOV Max Min 1.5V 1.5V Valid Max Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA TIH Valid 1.5V TIS TIH TIS BOFF 1.5V 1.5V 1.5V F_CX015A Figure 14. Bus Backoff (BOFF) Timings 32 80960CA-33, -25, -16 PCLK2:1 1.5V 1.5V 1.5V 1.5V ADS 1.5V TAVSH 1.5V A31:2, BE3:0, W/R, LOCK, SUP, D/C, DMA D31:0 1.5V 1.5V TNLQV TDVHN TNLNH Out 1.5V TNHQX 1.5V WAIT 1.5V TAVEL DT/R TEHTV DEN D31:0 1.5V 1.5V TVEL 1.5V In VIH VIL F_CX016A Figure 15. Relative Timings Waveforms 4.5.3 Derating Curves Output Valid Delays (ns) @ 1.5V nom + 10 nom + 5 All outputs except: LOCK, DMA, SUP, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL LOCK, DMA, SUP, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL nom 50 100 CL (pF) 150 F_CX017A Note: PCLK Load = 50pF Figure 16. Output Delay or Hold vs. Load Capacitance 33 80960CA-33, -25, -16 10 8 Time (ns) 6 4 2 50 0.8V to 2.0V 10 8 Time (ns) 6 4 2 100 CL (pF) 150 50 0.8V to 2.0V 100 CL (pF) 150 a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ DACK3:0, EOP3:0/TC3:0, FAIL b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL F_CX019A Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC 900 TC = 100 C ICC (mA) TC = 0 C 0 0 I CC - ICC under test conditions fPCLK (MHz) 33 F_CX020A Figure 18. ICC vs. Frequency and Temperature 34 80960CA-33, -25, -16 5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE Table 20 lists the condition of each processor output pin while HOLDA is asserted (low). Table 20. Hold Acknowledge and Backoff Conditions Pins A31:2 D31:0 BE3:0 W/R ADS WAIT BLAST DT/R DEN LOCK BREQ D/C DMA SUP FAIL DACK3:0 EOP3:0/TC3:0 State During HOLDA Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Driven (High or low) Floating Floating Floating Driven high (Inactive) Driven high (Inactive) Driven (If output) Table 19 lists the condition of each processor output pin while RESET is asserted (low). Table 19. Reset Conditions Pins A31:2 D31:0 BE3:0 W/R ADS WAIT BLAST DT/R DEN LOCK BREQ D/C DMA SUP FAIL DACK3:0 EOP3:0/TC3:0 State During Reset (HOLDA inactive)1 Floating Floating Driven high (Inactive) Driven low (Read) Driven high (Inactive) Driven high (Inactive) Driven low (Active) Driven low (Receive) Driven high (Inactive) Driven high (Inactive) Driven low (Inactive) Floating Floating Floating Driven low (Active) Driven high (Inactive) Floating (Set to input mode) NOTES: 1. With regard to bus output pin state only, the Hold Acknowledge state takes precedence over the reset state. Although asserting the RESET pin will internally reset the processor, the processor's bus output pins will not enter the reset state if it has granted Hold Acknowledge to a previous HOLD request (HOLDA is active). Furthermore, the processor will grant new HOLD requests and enter the Hold Acknowledge state even while in reset. For example, if HOLDA is inactive and the processor is in the reset state, then HOLD is asserted, the processor's bus pins enter the Hold Acknowledge state and HOLDA is granted. The processor will not be able to perform memory accesses until the HOLD request is removed, even if the RESET pin is brought high. This operation is provided to simplify boot-up synchronization among multiple processors sharing the same bus. 35 CLKIN 80960CA-33, -25, -16 VCC - ONCE VCC and CLKIN Stable to Outputs Valid, maximum 32 CLKIN Periods. BUS WAVEFORMS ADS, LOCK, WAIT, DEN, DACK3:0 BLAST Tdelay 1 PCLK D31:0, EOP/TC3:0 Inputs RESET CLKIN and VCC Stable to RESET high, minimum 32 CLKIN Periods in 2x Mode, 10,000 CLKIN periods in 1x Mode. RESET high to First Bus activity, approximately 32 PCLK periods. F_CX021A Tsetup 1PCLK Thold 1 PCLK STEST Valid Figure 19. Cold Reset Waveform INST, SUP, DMA, A31:2, D/C, BE3:0 W/R, DT/R, BREQ, FAIL PCLK2:1 36 6.0 Invalid ADS, LOCK, WAIT, DEN, DACK3:0 BLAST SUP, DMA, A31:2, D/C, BE3:0 Maximum RESET Low to RESET State 4 PCLK Periods RESET RESET High to First Bus Activity, Approximately 32 PCLK Periods Minimum RESET Low Time 16 PCLK Periods Tsetup 1 PCLK Thold 1 PCLK Valid Figure 20. Warm Reset Waveform D31:0, EOP/TC3:0 STEST Tdelay 1PCLK W/R, DT/R, BREQ, FAIL PCLK2:1 80960CA-33, -25, -16 37 F_CX022A 80960CA-33, -25, -16 CLKIN PCLK2:1 ADS, BE3:0, A31:2, D31:0, LOCK, WAIT, BLAST,W/R, D/C, DEN, DT/R, HOLD, HOLDA, BLAST, FAIL, SUP,BREQ, DMA, EOP3:0/TC3:0, STEST, XINT7:0, NMI, DACK3:0, DREQ3:0 READY, BTERM CLKIN and VCC Stable and RESET low and ONCE low to RESET high, minimum 32 CLKIN Periods in 2x Mode, 10,000 CLKIN Periods in 1x Mode. Figure 21. Entering the ONCE State ONCE RESET Maximum 32 CLKIN Periods Required after ONCE Mode entered VCC VCC and CLKIN Stable to Outputs Valid, maximum 32 CLKIN Periods. 38 CLKIN may not float. It must be driven high or low or continue to run F_CX023A 80960CA-33, -25, -16 CLKIN 1.5V 1.5V 1.5V 1.5V TIH TIS RESET 1.5V 1.5V PCLK2:1 (Case 1) Max Min PCLK2:1 (Case 2) 1.5V TCP 1.5V Max Min Min TCP Max 1.5V TCP 1.5V 1.5V SYNC 1.5V Note: Case 1 and Case 2 show two possible polarities of PCLK2:1 F_CX024A Figure 22. Clock Synchronization in the 2-x Clock Mode 2x CLK CLKIN 1.5V 1.5V TIH TIS RESET 1.5V Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising edge of CLKIN. The RESET pin is sampled when PCLK is high. F_CX025A Figure 23. Clock Synchronization in the 1-x Clock Mode 39 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 0 00000 N XDA 11-10 0 00 NRDD 9-8 X xx NRAD 7-3 0 00000 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Disabled 0 0 A PCLK D A D A D ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid Valid Valid W/R BLAST DT/R DEN A3:2 Valid Valid Valid WAIT D31:0 In Out In F_CX026A Figure 24. Non-Burst, Non-Pipelined Requests Without Wait States 40 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 1 01 NRDD 9-8 X xx NRAD 7-3 3 00011 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Disabled 0 0 A 3 2 1 D 1 A PCLK ADS A31:2, BE3:0 Valid W/R BLAST DT/R DEN DMA, D/C, SUP, LOCK Valid WAIT D31:0 In F_CX027A Figure 25. Non-Burst, Non-Pipelined Read Request With Wait States 41 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 3 00011 NXDA 11-10 1 01 NRDD 9-8 X xx NRAD 7-3 X xxxxxx PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Disabled 0 0 A 3 2 1 D 1 A PCLK ADS A31:2, BE3:0 Valid W/R BLAST DT/R DEN SUP, DMA, D/C, LOCK Valid WAIT D31:0 Out F_CX028A Figure 26. Non-Burst, Non-Pipelined Write Request With Wait States 42 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-Bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 0 00 NRDD 9-8 0 00 NRAD 7-3 0 00000 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A PCLK D D D D A ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 In0 In1 In2 In3 F_CX029A Figure 27. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus 43 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 1 01 NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 D 1 A PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 In0 In1 In2 In3 F_CX030A Figure 28. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus 44 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 0 00 NWAD 16-12 0 00000 NXDA 11-10 0 00 NRDD 9-8 X xx NRAD 7-3 X xxxxx PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A PCLK D D D D A ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 Out0 Out1 Out2 Out3 F_CX031A Figure 29. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus 45 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 1 01 NWAD 16-12 2 00010 NXDA 11-10 1 01 NRDD 9-8 X xx NRAD 7-3 X xxxxx PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 D 1 A PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 Out0 Out1 Out2 Out3 F_CX032A Figure 30. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus 46 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 16-bit 01 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 1 01 NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 D 1 A PCLK ADS SUP, DMA, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE W/R Valid BLAST DT/R DEN A3:2 A3:2 = 00 or 10 A3:2 = 01 or 11 BE1/A1 WAIT D31:0 D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 D15:0 A1=1 F_CX033A Figure 31. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus 47 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 8-bit 00 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 1 01 NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 D 1 A PCLK ADS SUP, DMA, D/C, LOCK, A31:4 Valid W/R BLAST DT/R DEN A3:2 A3:2 = 00, 01, 10 or 11 BE1/A1, BE0/A0 A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 =11 WAIT D31:0 D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 F_CX034A Figure 32. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus 48 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 X xx NRAD 7-3 0 00000 PipeLining 2 ON 1 External Ready Control 1 X x Burst 0 Disabled 0 31-23 0 0..0 21 0 0 A A' D A'' D' A''' D'' A'''' D''' D'''' PCLK ADS A31:4, SUP, DMA, D/C, LOCK Valid Valid Valid Valid Valid Invalid W/R Invalid A3:2 BE3:0 Valid Valid Valid Valid Valid Invalid D31:0 IN D IN D' IN D'' IN D''' IN D'''' WAIT BLAST DT/R DEN Non-Pipelined Request Concludes Pipelined Reads Begin. Pipelined Reads Conclude, Non-Pipelined Requests Begin. F_CX035A Figure 33. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus 49 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 X xx NRAD 7-3 1 00001 PipeLining 2 ON 1 External Ready Control 1 X x Burst 0 Disabled 1 31-23 0 0..0 21 0 0 A 1 A' D 1 D' PCLK ADS A31:4, SUP, DMA, D/C, LOCK Valid Valid Invalid W/R Invalid A3:2 BE3:0 Valid Valid Invalid D31:0 IN D IN D' WAIT BLAST DT/R DEN Non-Pipelined Request Concludes Pipelined Reads Begin. Pipelined Reads Conclude, Non-Pipelined Requests Begin. F_CX036A Figure 34. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus 50 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 0 00 NRAD 7-3 0 00000 PipeLining 2 ON 1 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A D D D A' D D' D' PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid Valid InValid W/R InValid A3:2 00 01 10 11 Valid Valid InValid D31:0 IN D IN D IN D IN D IN D IN D WAIT BLAST DT/R DEN Non-pipelined Request Concludes, Pipelined Reads Begin Pipelined Reads Conclude, Non-Pipelined Requests Begin F_CX037A Figure 35. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus 51 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 ON 1 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 A' D 2 1 D' PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid Valid Invalid W/R Invalid A3:2 00 01 10 11 Valid Invalid D31:0 IN D IN D IN D IN D IN D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, Non-pipelined requests begin. F_CX038A Figure 36. Burst, Pipelined Read Request With Wait States, 32-Bit Bus 52 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 16-bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 ON 1 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 A' D 2 1 D' PCLK ADS A31:4, SUP, DMA, D/C, BE0/BLE, BE3/BHE, LOCK W/R Valid Valid Invalid Invalid A3:2 A3:2 = 00 or 10 A3:2 = 01 or 11 Valid Invalid BE1/A1 Valid Invalid D31:0 D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 D15:0 A1=1 D15:0 D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, Non-pipelined requests begin. F_CX040A Figure 37. Burst, Pipelined Read Request With Wait States, 16-Bit Bus 53 80960CA-33, -25, -16 reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 8-bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 ON 1 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 A' D 2 1 D' PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R Valid Valid Invalid Invalid Invalid A3:2 A3:2 = 00, 01, 10, or 11 Valid BE1/A1, BE0/A0 A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 = 11 Valid Invalid D31:0 D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 D7:0 D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, Non-pipelined requests begin. F_CX039A Figure 38. Burst, Pipelined Read Request With Wait States, 8-Bit Bus 54 80960CA-33, -25, -16 Quad-Word Read Request NRAD = 0, NRDD = 0, NXDA = 0 Ready Enabled Quad-Word Write Request NWAD = 1, NWDD = 0, NWDA = 0 Ready Enabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK W/R Valid Valid BLAST DT/R DEN READY BTERM A3:2 00 01 10 11 00 01 10 11 WAIT D31:0 D0 D1 D2 D3 D0 D1 D2 D3 F_CX041A Figure 39. Using External READY 55 80960CA-33, -25, -16 Quad-Word Write Request NWAD = 0, NWDD = 0, NWDA = 0 Ready Enabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN READY See Note BTERM A3:2 00 01 10 11 WAIT D31:0 D0 D1 D2 D3 Note: READY adds memory access time to data transfers, whether or not the bus access is a burst access. BTERM interrupts a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. F_CX042A Figure 40. Terminating a Burst with BTERM 56 80960CA-33, -25, -16 Regenerate ADS ADS BURST BURST MAY CHANGE BLAST NON-BURST READY BOFF A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R D31:0, (WRITES) SUSPEND REQUEST Begin Request BOFF May be asserted to suspend request BOFF may not be asserted Note: READY/BTERM must be enabled; NRAD, NRDD, NWAD, NWDD= 0 End Request BOFF may not be asserted F_CX043A Figure 41. BOFF Functional Timing RESUME REQUEST 57 80960CA-33, -25, -16 Word Read Request NRAD=1, NXDA=1 Hold State Word Read Request NRAD=0, NXDA=0 Hold State PCLK2:1 ADS A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R Valid Valid BLAST HOLD HOLDA F_CX044A Figure 42. HOLD Functional Timing 58 80960CA-33, -25, -16 PCLK2:1 System Clock Start DMA Bus Request End of DMA Bus Request ADS ! (BLAST & READY & !WAIT) DACKx (All Modes) DREQx (Case 1) (See Note) DMA Acknowledge High To Prevent Next Bus Cycle tIS5 tIH5 High To Prevent Next Bus Cycle tIS5 tIH5 DMA Request DREQx (Case 2) Note: 1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-By and some packing and unpacking modes in which loads are followed by loads or stores are followed by stores. 2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high. Applications are non Fly-By transfers and adjacent load-stores or store-loads. 3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus accesses (defined by ADS and BLAST. Refer to i960(R) Cx Microprocessor User's Manual for "access", "request" definitions. F_CX018A Figure 43. DREQ and DACK Functional Timing EOP 2 CLKs Min 15 CLKs Max Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge triggered. EOP must be held for a minimum of 2 clock cycles then deasserted within 15 clock cycles. F_CX045A Figure 44. EOP Functional Timing 59 PCLK2:1 80960CA-33, -25, -16 PCLK2 DREQ ADS DACK TC Note: Terminal Count becomes active during the last bus request of a buffer transfer. If the last LOAD/STORE bus request is executed as multiple bus accesses, the TC will be active for the entire bus request. Refer to the i960(R) Cx Microprocessor User's Manual for further information. F_CX046A Figure 45. Terminal Count Functional Timing RESET (Internal Self-Test) Pass (Bus Test) Pass ~65,000 Cycles Fail 5 Cycles FAIL Fail F_CX047A 102 Cycles Figure 46. FAIL Functional Timing 60 80960CA-33, -25, -16 Byte Offset 0 4 8 12 16 20 24 Word Offset 0 1 2 3 4 5 6 Short Request (Aligned) Byte, Byte Requests Short-Word Load/Store Short Request (Aligned) Byte, Byte Requests Word Request (Aligned) Byte, Short, Byte, Requests Word Load/Store Short, Short Requests Byte, Short, Byte Requests One Double-Word Burst (Aligned) Byte, Short, Word, Byte Requests Short, Word, Short Requests Double-Word Load/Store Byte, Word, Short, Byte Requests Word, Word Requests One Double-Word Request (Aligned) F_CX048A Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Regions 61 80960CA-33, -25, -16 0 Byte Offset 0 4 8 12 16 20 24 Word Offset 1 2 3 4 One Three-Word Request (Aligned) Byte, Short, Word, Word, Byte Requests 5 6 Triple-Word Load/Store Short, Word, Word, Short Requests Byte, Word, Word, Short, Byte Requests Word, Word, Word Requests Word, Word, Word Requests Word, Word, Word Requests One Four-Word Request (Aligned) Byte, Short, Word, Word, Word, Byte Requests Quad-Word Load/Store Short, Word, Word, Word, Short Requests Byte, Word, Word, Word, Short, Byte Requests Word, Word, Word, Word Requests DoubleWord, DoubleWord, Requests F_CX049A Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) 62 80960CA-33, -25, -16 Write Request NWAD=2, NXDA = 0 Ready Disabled Idle Bus (not in Hold Acknowledge state) Read Request NWAD=2, NXDA = 0 Ready Disabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0 LOCK Valid Valid Valid Valid W/R BLAST DT/R DEN A3:2 Valid Valid WAIT D31:0 Out In READY, BTERM F_CX050A Figure 49. Idle Bus Operation 63 80960CA-33, -25, -16 7.0 REVISION HISTORY This data sheet supersedes data sheet 270727-005. Specification changes in the 80960CA data sheet are a result of design changes. The sections significantly changed since the previous revision are: Section Table 11. 80960CA PGA Package Thermal Characteristics Table 12. 80960CA PQFP package Thermal Characteristics 3.3 80960CA Mechanical Data Last Rev. -005 -005 -005 Description Removed references and notes pertaining to J-CAP and J-PIN. Removed references and notes pertaining to JL and JB. Removed section containing information on Package Dimensions. Moved section header to encompass Pinout tables and diagrams. Removed entire section containing information about 80960CA accessories. TTVEL maximum deleted. TNHQX and TEHTV minimums changed: WAS: TNHQX TEHTV All -005 (N+1)*T-6 T/2 - 6 IS: (N+1)*T-8 T/2 - 7 3.7 Suggested Sources for 80960CA Accessories Tables 16, 17 and18 80960CA AC Characteristics (33-, 25- and 16MHz, respectively) -005 -005 All timing diagrams and waveforms have been redrawn to conform to consistent format. Data sheet formatting has been changed to conform to corporate standards. Specific formatting changes are not itemized in this revision history. 64 |
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